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AIDigest/2026/07/28/2026-07-28-06-nvidia-vera-cpu-eda

NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs

Source: NVIDIA Blog — 2026-07-27

Summary

NVIDIA is now deploying its own Vera CPU — 88 custom NVIDIA Olympus cores paired with LPDDR5X memory and second-generation NVIDIA Scalable Coherent Fabric — internally within its electronic design automation (EDA) workflows to help design its next generation of CPUs and GPUs. In testing, Cadence Jasper (formal verification, which checks a chip design against its specification) and Synopsys VCS (functional simulation used to validate designs pre-fabrication) both showed up to 1.5x higher performance on selected NVIDIA production workloads when run on Vera. Separately, Synopsys is building its AgentEngineer autonomous workflow tooling on the NVIDIA Agent Toolkit, NIM microservices, Nemotron open models, NeMo Gym, and NemoClaw blueprints to run longer, more autonomous agentic chip-design workflows.

Key Takeaways

  • NVIDIA is using its own Vera CPU (88 Olympus cores, LPDDR5X memory, 2nd-gen NVIDIA Scalable Coherent Fabric) inside its own EDA pipeline to design future chips — a "designing chips with your own chips" feedback loop.
  • Cadence Jasper (formal verification) and Synopsys VCS (functional simulation) both measured up to 1.5x performance improvement on selected NVIDIA production workloads when moved to Vera.
  • Faster verification and simulation directly shortens individual job runtimes and increases throughput across large regression-testing farms, which are typically a major bottleneck in chip development schedules.
  • Synopsys AgentEngineer is being built on the NVIDIA Agent Toolkit, NIM microservices, Nemotron open models, NeMo Gym, and NemoClaw blueprints to support longer-running, more autonomous agentic workflows across chip and system design.
  • The announcement is framed primarily as an internal case study and ecosystem-partner rollout (Cadence and Synopsys tools optimized for Vera) rather than a new technical mechanism — it demonstrates adoption and measured speedups more than it introduces a novel, diagrammable system.

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